1. Field of the Invention
This invention relates to the extraction of information from a PCM data stream. In a particular application the invention can be used to extract information in a Synchronous Digital Hierarchy (SDH) transmission system.
2. Description of the Prior Art
The extraction of information from such a system can be equated to the recovery of clock signals from a data stream composed of signals from a plurality of clock sources.
In an SDH system the data stream may include e.g. frame clocks, byte clocks, and bit clocks each conveying different manifestations of information.
Within the known SDH range of equipment described in CCITT recommendations G707, 708 and 709 there is provision for possible clock frequency differences caused by the plesiochronous nature of the digital telephone network. These differences are processed using a so-called floating mode of operation within the hierarchy, as described in the aforementioned CCITT (International Consultive Committee for Telephone and Telegraph) recommendation G709. With the floating mode of operation two methods of data rate justification are used for clock correction, viz. Byte mode justification for those clock differences apparent within a network of SDH equipment; and bit mode justification for those clock differences apparent at tributary interface points where external networks connect to the SDH equipment network. The resultant sum of these justification processes must be processed at the tributary output ports and this is usually done using one or more elastic stores (FIFO) together with phase locked read clocks to prevent loss of data while attenuating framing and justification jitter present at the tributary output ports. The store can be implemented also by other suitable known stores such as a RAM. In one embodiment the invention may be used to handle packet data where different packets may arrive out of order due to different transmission paths. In such a case the store could be implemented by the use of a RAM from which the packet data could be read out in the correct sequence.
Designs presently exist for phase locked loops which provide filtering means similar to that required by SDH equipment (see British Telecom's submission T1X1 6/89 entitled "SONET Desynchronisers") but these designs are either excessively complex or lack flexibility in processing the dual justification referred to above.
Each of the two aforementioned justification methods have different requirements; the first justification method, being byte mode in nature, but restricted within the SDH network where clock frequency differences will be small, will have characteristics of low frequency large amplitude (8 bit) phase hits which require considerable smoothing to maintain performance required by equipment having interfaces designed in accordance with CCITT G703 recommendations and jitter tolerance specifications in accordance with limits set in the CCITT G823 recommendations. The second justification method, being bit mode in nature, and having characteristics of the network external to the SDH network, requires a fast response time enabling quick settling times from transient error and changeover related conditions occurring outside the SDH equipment.
The aforementioned British Telecom submission proposes dual elastic stores and phase locked oscillators to provide these dual justification processing methods, but the complexity of the circuitry required to implement the arrangement proposed in the British Telecom submission is obvious.
It will be understood that compromise arrangements can be designed which have simpler circuitry but performance will be sacrificed. For example a single phase locked loop could be utilized but it would require filter characteristics to meet the most severe jitter source equivalent to the Byte Mode justification referred to above. Speed of response and settling time imposed on the smoothing of the bit mode justification would be sacrificed.